`timescale 100ns/100ns
module top1_tb (
    
);

reg clk,rstn;
wire q;
top1 top1(
     .rstn(rstn)
    ,.clk(clk)
    ,.q(q)
);

initial begin
   clk = 1'b0;
   rstn = 1'b0;
 end

always  begin
    #20 rstn = 1'b1;
    #20 rstn = 1'b0;
    #20 rstn = 1'b1;
    #500000;
end

always  begin
  #5 clk = ~clk;
end
endmodule //top1_tb